Since the invention of the integrated circuit (IC), the semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than previous packages. Some smaller types of packages for semiconductor devices include quad flat pack (QFP), pin grid array (PGA), ball grid array (BGA), flip chips (FC), three dimensional integrated circuits (3DIC), wafer level packages (WLP), wafer-level chip scale packages (WLCSP), and package on package (PoP) devices.
Under-bump metallization (UBM) layers are used in semiconductor device packages for flip-chips, WLP, WLCSP, 3DIC, and many advanced package technology fields. In a typical bumping process, interconnect structures are formed on metallization layers, followed by the formation of UBM layers and solder balls to establish electrical contacts between contact pads of a chip such as input/output pads and the substrate or lead frame of the package.
Current processes for making UBM layers can induce UBM undercuts, which increase silicon inter-metal material delamination risk. UBM undercuts further reduce the effective UBM pad sizes and therefore reduce the package reliability. Methods and devices are needed to reduce the UBM undercuts during the UBM bumping process.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.